integrated circuit systems, inc. ics9248-65 block diagram frequency timing generator for pentium ii systems 9248-65 rev c 7/28/99 pin configuration 48-pin ssop ? generates the following system clocks: - 3 cpu clocks ( 2.5v, 100/133mhz) - 10 pci clocks, including 1 free-running (3.3v, 33.3mhz) - 1 cpu/2 clocks (2.5v, 50/66.6mhz) - 1 ioapic clocks (2.5v, 16.67mhz) - 3 fixed frequency 66mhz clocks(3.3v, 66.6mhz) - 2 ref clocks(3.3v, 14.318mhz) - 1 usb clock (3.3v, 48mhz) ? efficient power management through pd#. ? 0 to -0.5% typical down spread modulation on cpu, pci, ioapic, 3v66 and cpu/2 output clocks. ? uses external 14.318mhz crystal. ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. features key specification ? cpu output jitter: <250ps ? cpu/2 output jitter. <250ps ? ioapic output jitter: <500ps ? 48mhz, 3v66, pci output jitter: <500ps ? pci output jitter. <500ps ? ref output jitter. <1000ps ? cpu 0:2 output skew: <175ps ? pci_f, pci 1:7 output skew: <500ps ? 3v66_0:2 output skew <250ps ? cpu to 3v66_0:2 output offset: 0.0 - 1.5ns (cpu leads) ? 3v66 to pci output offset: 1.5 - 4ns (cpu leads) ? cpu to ioapic output offset 1.5 - 4.0ns (cpu leads)
2 ics9248-65 pin descriptions pin number pin name type description 1,2 ref output 3.3v, 14.318 mhz reference clock output. 3, 9, 17, 24, 28, 34 vdd power 3.3 v power for clock outputs. 4 x1 input 14.318 mhz crystal input 5 x2 output 14.318 mhz crystal output 6,14, 20, 26, 33, 45, 48 gnd power ground for clock outputs 7 pciclk_f output 3.3 v free running pci clock output, will not be stopped by the pci_stop# 8,10,11,12,13, 15,16,18,19 pciclk (1:9) output 3.3 v pci clock outputs, generating timing requirements for 21,22,23 3v66 output 3.3 v 66 mhz clock output, fixed frequency clock typically used with agp 25 sel 133/100# input control for the frequency of clocks at the cpu output pins. if logic "0" is used the 100 mhz frequency is selected. if logic "1" is used, the 133 mhz frequency is selected. the pci clock is multiplexed to run at 33.3 mhz for both selected cases. 27 48 mhz output 3.3 v 48 mhz clock output, fixed frequency clock typically used with usb devices 29,30 sel (0:1) input frequency select pin , logic input. 31 spread# output power-on spread spectrum enable option. active low = spread spectrum clocking enable. active high = spread spectrum clocking disable. 32 pd# input asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. 35,39 gndlcpu power ground for the cpu and host clock outputs 36,37,40 cpuclk (0:2) 0utput 2.5 v cpu and host clock outputs 38,41 vddlcpu power 2.5 v power for the cpu and host clock outputs 42 gndlcpu/2 power ground for the cpu and host clock outputs 43 cpu/2 output output running at 1/2 cpu clock frequency.synchronous to the cpu outputs. 44 vddlcpu/2 power 2.5 v power for the cpu/2 clock outputs 46 ioapic(0:1) output 2.5v fixed 16.6 mhz ioapic clock outputs 47 vddioapic power 2.5v power for ioapic clock the ics9248-65 is a main clock synthesizer chip for pentium ii based systems using rambus interface drams. this chip provides all the clocks required for such a system when used with a direct rambus clock generator(drcg) chip such as the ics9211-01. spread spectrum may be enabled by driving the spread# pin active. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248-65 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. the cpu/2 clocks are inputs to the drcg. general description power groups: vddref, gndref = ref, x1, x2 gndpci, vddpci = pciclk vdd66, gnd66 = 3v66 vdd48, gnd48 = 48mhz vddcor, gndcor = pll core vddlcpu/2 , gndlcpu/2 = cpu/2 vddlioapic, gndioapic = ioapic
3 ics9248-65 frequency select: note: 1. tclk is a test clock driven on the x1 input during test mode. ics9248-65 power management features: note: 1. low means outputs held static low as per latency requirement next page. 2. on means active. 3. pd# pulled low, impacts all outputs including ref and 48 mhz outputs. l e s # 0 0 1 / 3 3 1 1 l e s0 l e s u p c z h m 2 / u p c z h m 6 6 v 3 z h m i c p z h m 8 4 z h m f e r z h m c i p a o i z h m s t n e m m o c 000 z - i hz - i hz - i hz - i hz - i hz - i hz - i he t a t s - i r t 001 a / na / na / na / na / na / na / nd e v r e s e r 010 0 0 10 56 . 6 63 . 3 3z - i h8 1 3 . 4 17 6 . 6 1 l l p z h m 8 4 d e l b a s i d 011 0 0 10 56 . 6 63 . 3 38 48 1 3 . 4 17 6 . 6 1 100 2 / k l c t4 / k l c t4 / k l c t8 / k l c t2 / k l c tk l c t6 1 / k l c t) 1 ( e d o m t s e t 101 a / na / na / na / na / na / na / nd e v r e s e r 110 3 . 3 3 16 66 63 3z - i h8 1 3 . 4 17 6 . 6 1 111 3 . 3 3 16 66 63 38 48 1 3 . 4 17 6 . 6 1 # d pk l c u p c2 / u p cc i p a o i6 6 v 3i c pf _ i c p . f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on on o power management requirements: note: 1. clock on/off latency is defined in the number of rising edges of free running pciclks between the clock disable goes low/ high to the first valid clock comes out of the device. 2. power up latency is when pwr_dwn# goes inactive (high to when the first valid clocks are dirven from the device. l a g n i se t a t s l a g n i s y c n e t a l s e g d e g n i s i r f o . o n k l c i c p f o # d p ) n o i t a r e p o l a m r o n ( 1s m 3 ) n w o d r e w o p ( 0. x a m 2
4 ics9248-65 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz.
5 ics9248-65 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = vddl = 3.3 v +/-5%, (unless otherwis e s tated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 m a i dd3.3op100 c l = 0 pf; select @ 100 mhz 65 i dd3.3op133 c l = 0 pf; select @ 133.3 mhz 71 i dd3.3op144 c l = 0 pf; select @ 144 mhz 75 i dd3.3op154 c l = 0 pf; select @ 154 mhz 78 power down i dd3.3pd c l = 0 pf; pwrdwn# = 0 64 200 m a supply current input frequency f i v dd = 3.3 v 12 14.318 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 1 3 ms settling time 1 t s from 1st crossing to 1% target freq. 0.5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cpu-pci v t = 1.5 v; v tl = 1.25 v 1.5 2.4 4 ns skew 1 t cpu-3v66 v t = 1.5 v; v tl = 1.25 v 1.4 1.5 ns skew 1 t 3v66-pci v t = 1.5 v 1.4 4 ns 1 guaranteed by design, not 100% tested in production. operating 160 ma group offset group offset measurement loads measure points cpu to 3v66 0.0-1.5ns cpu leads cpu @ 20pf, 3v66 @ 30pf cpu @1.25v, 3v66 @ 1.5v 3v66 to pci 1.5-4.0ns 3v66 leads 3v66 @ 30pf, pci @ 30pf 3v66 @ 1.5v, pci @ 1.5v cpu to ioapic 1.5-4.0ns cpu leads cpu @ 20pf, ioapic @ 20pf cpu @1.25v, ioapic @ 1.5v note: 1. all offsets are to be measured at rising edges.
6 ics9248-65 electrical characteristics - input/supply/common output parameter s t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units i dd2.5op100 c l = 0 pf; select @ 100 mhz 14 30 operating i dd2.5op133 c l = 0 pf; select @ 133.3 mhz 18 30 supply current i dd2.5op144 c l = 0 pf; select @ 144 mhz 19 30 i dd2.5op154 c l = 0 pf; select @ 154 mhz 20 30 power down i dd2.5pd c l = 0 pf; pwrdwn# = 0 0.3 100 m a supply current skew 1 t cpu-pci v t = 1.5 v; v tl = 1.25 v 1.5 2.4 4 ns skew 1 t cp u-3v66 v t = 1.5 v; v tl = 1.25 v 1.4 1.5 ns skew 1 t cpu-ioapic v tl = 1.25 v 1.4 4 ns 1 guaranteed by design, not 100% tested in production. ma electrical characteristics - cpuclk t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.3 v output low voltage v ol2 b i ol = 12 ma 0.31 0.4 v output high current i oh2 b v oh = 1.7 v -39 -19 ma output low current i ol2 b v ol = 0.7 v 19 27 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.95 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v, freq. < 124 mhz 45 50 55 % skew t sk2b 1 v t = 1.25 v 22 175 ps jitter, one sigma t j1 s 2b 1 v t = 1.25 v 21 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 55 +250 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 110 250 ps 1 guaranteed by design, not 100% tested in production.
7 ics9248-65 electrical characteristics - cpu/2 t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.3 v output low voltage v ol2 b i ol = 12 ma 0.31 0.4 v output high current i oh2 b v oh = 1.7 v -33 -19 ma output low current i ol2 b v ol = 0.7 v 19 27 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.1 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v, freq. < 124 mhz 45 48 55 % jitter, one sigma t j1 s 2b 1 v t = 1.25 v 13 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 42 +250 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 100 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - 3v66 t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.17 0.4 v output high current i oh1 v oh = 2.0 v -61 -22 ma output low current i ol1 v ol = 0.8 v 25 45 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.8 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.7 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51 55 % skew 1 t sk1 v t = 1.5 v 37 500 ps jitter, one sigma 1 t j1 s 1 v t = 1.5 v 16 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 50 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 130 500 ps 1 guaranteed by design, not 100% tested in production.
8 ics9248-65 electrical characteristics - pciclk t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.17 0.4 v output high current i oh1 v oh = 2.0 v -62 -22 ma output low current i ol1 v ol = 0.8 v 25 45 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.6 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 310 500 ps jitter, one sigma 1 t j1 s 1 v t = 1.5 v 11 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 45 250 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 105 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -12 ma 2 2.4 v output low voltage v ol4b i ol = 12 ma 0.17 0.4 v output high current i oh4b v oh = 1.7 v -61 -19 ma output low current i ol4b v ol = 0.7 v 19 53 ma ris e time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.75 2.2 ns fall time 1 t f4 b v oh = 2.0 v, v ol = 0.4 v 0.675 2 ns duty cycle 1 d t4b v t = 1.25 v 45 49.5 55 % jitter, one sigma 1 t j1 s 4b v t = 1.25 v 26 150 ps jitter, absolute 1 t jabs4b v t = 1.25 v -500 137 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 200 500 ps 1 guaranteed by design, not 100% tested in production.
9 ics9248-65 electrical characteristics - ref, 48mhz t a = 0 - 70o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.4 2.9 v output low voltage v ol5 i ol = 10 ma 0.33 0.4 v output high current i oh5 v oh = 2.0 v -31 -22 ma output low current i ol5 v ol = 0.8 v 16 23 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.8 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 2.1 4 ns duty cycle 1 d t5 v t = 1.5 v 45 52 55 % jitter, one sigma 1 t j1 s 5 v t = 1.5 v, ref 85 150 ps jitter, absolute 1 t jabs5 v t = 1.5 v, ref -500 285 500 ps jitter, one sigma 1 t j1 s 5 v t = 1.5 v, 48 mhz 32 150 ps jitter, absolute 1 t jabs5 v t = 1.5 v, 48 mhz -250 110 250 ps 1 guaranteed by design, not 100% tested in production.
10 ics9248-65 l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . 48 pin ssop package ordering information ics9248 y f-65 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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